Reduction Operators – Verilog Example

The Verilog reduction operators are used to convert vectors to scalars. They operate on all of the bits in a vector to convert the answer to a single bit. The logic performed on the bit-vectors behaves the same way that normal AND, NAND, OR, NOR, XOR, and XNOR Gates behave inside of an FPGA. The code below demonstrates the usage of the Verilog reduction operator.

reduction_operators.v:

module reduction_operators ();

  reg r_C;
  
  // Initial statement is not synthesizable (test code only)
  initial
    begin
      #10;
      $display("AND  Reduction of 4'b1101 is: %b", &4'b1101);
      $display("AND  Reduction of 4'b1111 is: %b", &4'b1111);

      $display("NAND Reduction of 4'b1101 is: %b", ~&4'b1101);
      $display("NAND Reduction of 4'b1111 is: %b", ~&4'b1111);

      $display("OR   Reduction of 4'b1101 is: %b", |4'b1101);
      $display("OR   Reduction of 4'b0000 is: %b", |4'b0000);
      
      $display("NOR  Reduction of 4'b1101 is: %b", ~|4'b1101);
      $display("NOR  Reduction of 4'b0000 is: %b", ~|4'b0000);
      
      $display("XOR  Reduction of 4'b1101 is: %b", ^4'b1101);
      $display("XOR  Reduction of 4'b0000 is: %b", ^4'b0000);
      
      $display("XNOR Reduction of 4'b1101 is: %b", ~^4'b1101);
      $display("XNOR Reduction of 4'b0000 is: %b", ~^4'b0000);
      
      // A bitwise reduction can be stored in another reg.
      r_C = |4'b0010;

      $display("Reduction of 4'b0010 stored into a reg is: %b", r_C);

    end
endmodule // reduction_operators

Modelsim Console Output:

# AND  Reduction of 4'b1101 is: 0
# AND  Reduction of 4'b1111 is: 1
# NAND Reduction of 4'b1101 is: 1
# NAND Reduction of 4'b1111 is: 0
# OR   Reduction of 4'b1101 is: 1
# OR   Reduction of 4'b0000 is: 0
# NOR  Reduction of 4'b1101 is: 0
# NOR  Reduction of 4'b0000 is: 1
# XOR  Reduction of 4'b1101 is: 1
# XOR  Reduction of 4'b0000 is: 0
# XNOR Reduction of 4'b1101 is: 0
# XNOR Reduction of 4'b0000 is: 1
# Reduction of 4'b0010 stored into a reg is: 1