Logical Operators – Verilog Example

Logical operators are fundamental to Verilog code. The logical operators that are built into Verilog are:

Logical operators are most often used in if else statements. They should not be confused with bitwise operators such as &, |, ~, ^, and ^~. These logical operators can be combined on a single line. Parenthesis will dictate the order of operations. For example the line:

(b || c) && (d || e)

will first perform a Logical Or of signals b and c, then perform a Logical Or of signals d and e, then perform a Logical And of the results of the two operations. All of the logical operators are synthesizable. If any inputs are unknown (X) the output will also be unknown. Verilog will not throw an error if a vector is used as an input to the logical operator, however the code will likely not work as intended. It is recommended to first use the reduction operator on a vector to turn it into a scalar before using a logical operator.

Below is the console output from running the code below in Modelsim:

# Either r_A or r_B is 1
# r_A and r_B are not both 1
# r_A is 1

logical_operators.v:

module logical_operators ();

  reg r_A = 1'b1;
  reg r_B = 1'b0;

  // Initial statement is not synthesizable (test code only)
  initial
    begin
      #10;
      if (r_A || r_B)
        $display("Either r_A or r_B is 1");
      else
        $display("Neither r_A or r_B is 1");
      
      if (r_A && r_B)
        $display("Both r_A and r_B are 1");
      else
        $display("r_A and r_B are not both 1");

      if (!r_A)
        $display("r_A is not 1");
      else
        $display("r_A is 1");
    end
endmodule // logical_operators