Function – Verilog Example

Write synthesizable and automatic functions in Verilog

Functions are sections of Verilog code that allow the Digital Designer to write more reusable and maintainable code. Often a function is created when the same operation is done over and over throughout Verilog code. Rather than rewriting code, one can just call the function. This prevents copy and paste errors and allows for more maintainable code: if the behavior of the function changes, it only needs to be updated in one location.

One rule about functions is that they cannot have any time delay (# delay, posedge). This is one way in which they differ from tasks. For this reason, functions are used for creating combinational logic. Yes, functions are synthesizable!

Below is a list of rules for functions:

• Functions can have any number of inputs but only one output (one return value)
• The order of inputs to a function dictates how it should be wired up when called
• The return type defaults to one bit unless defined otherwise
• Functions execute immediately (zero time delay)
• Functions can call other functions but they cannot call tasks
• Functions can drive global variables external to the function
• Variables declared inside a function are local to that function
• Non-blocking assignment in function is illegal
• Functions can be automatic (see below for more detail)

Often functions are created in the file they are used in. The example below demonstrates this. However functions can also be included via the `include compile directive.

function_example.v

module function_example ();

  reg r_Bit1=1'b1, r_Bit2=1'b0, r_Bit3=1'b1;
  wire w_Result;
  reg  r_Global;

  function do_math;
    input i_bit1, i_bit2, i_bit3; 
    reg   v_Temp; // Local Variable
    begin
      // Demonstrates driving external Global Reg
      r_Global = 1'b1; 
      
      v_Temp  = (i_bit1 & i_bit2);
      do_math = (v_Temp | i_bit3);
    end
  endfunction

  assign w_Result = do_math(r_Bit1, r_Bit2, r_Bit3);

endmodule

---

Automatic Functions

Functions can be declared as automatic functions as of Verilog 2001.

function automatic do_math;

Automatic is a term borrowed from C which allows the function to be re-entrant. A re-entrant function is one in which the items declared within the function are allocated upon every individual call of the function, as opposed to being shared between all calls of the function. This could be a problem in a simulation environment if code is forked and calls the same function at the same time. Race conditions can develop.

In C, all variables are automatic by default. In order to make them not automatic, they must be declared as static. Verilog is the opposite with functions. All functions are static by default and should be declared automatic if they are called simultaneously. A good practice is to declare your functions as automatic by default. The keyword automatic also allows you to write recursive functions, since now the simulator can dynamically allocate as many copies of the internal variables as it needs to unroll the recursion. The example below demonstrates how recursion can be used in an automatic function.

module function_auto ();

  function automatic [7:0] factorial;
    input [7:0] i_Num; 
    begin
      if (i_Num == 1)
        factorial = 1; 
      else
        factorial = i_Num * factorial(i_Num-1);
    end
  endfunction

  initial 
    begin
      $display("Factorial of 1 = %d", factorial(1));
      $display("Factorial of 2 = %d", factorial(2));
      $display("Factorial of 3 = %d", factorial(3));
      $display("Factorial of 4 = %d", factorial(4));
      $display("Factorial of 5 = %d", factorial(5));
    end
endmodule

Console Result from Modelsim Simulation:
# Factorial of 1 =   1
# Factorial of 2 =   2
# Factorial of 3 =   6
# Factorial of 4 =  24
# Factorial of 5 = 120