Forever Loop – Verilog Example

The keyword forever in Verilog creates a block of code that will run continuously. It is similar to other loops in Verilog such as for loops and while loops. The main difference between these and the forever loop is that the forever loop will never stop running, whereas for and while have a limit.

Forever Loops should not be used in synthesizable code. They are intended for use in simulation testbenches only. Forever loops are most useful within tasks. This allows a task to perform some functionality until the simulation is quit. Note that the Jump Statements return and break can be used to exit your loop prematurely, but these are only supported in SystemVerilog.

Make sure that your forever loop takes some delta time or it could hang your simulation!

forever_ex.v:

module forever_ex (); 

  reg r_Clock = 1'b0;
  
  initial 
    begin
      forever
        #10 r_Clock = !r_Clock;
    end 
 
endmodule