Shift Operator <<, >>, Verilog Example

Create shift registers, shift left, shift right in your FPGA or ASIC

The shift operator in Verilog is used to shift data in a variable. The left hand side of the operator contains the variable to shift, the right hand side of the operator contains the number of shifts to perform. The shift operator is a quick way to create a Shift Register.

The normal shifts << and >> shift your input and pad with zeros. The arithmetic shift >>> preserves the sign of the MSB of your variable. This is useful for inputs that are signed (can be positive or negative). In practice, <<< and << behave the same.

shift_operator.v:

module shift_operator (); 

  reg        [3:0] r_Shift1 = 4'b1000;
  reg signed [3:0] r_Shift2 = 4'b1000;
  
  initial 
    begin
      // Left Shift
      $display("%b", r_Shift1 <<  1);
      $display("%b", $signed(r_Shift1) <<< 1); // Cast as signed
      $display("%b", r_Shift2 <<< 1); // Declared as signed type // Right Shift $display("%b", r_Shift1 >>  2);
      $display("%b", $signed(r_Shift1) >>> 2); // Cast as signed
      $display("%b", r_Shift2 >>> 2) ;         // Declared as signed type
    end
endmodule 

Simulation Output
# 0000
# 0000
# 0000
# 0010
# 1110
# 1110

Shifting to Create a Shift Register

Below is Verilog code showing how to create a shift register. Shift registers are very important for aligning data in your FPGA. The shift operator makes this code clean and compact. The shift register is 4 clock cycles long. It will delay any input by 4 clock cycles. Later on in your code, if you look for Input_Delay[3] it will show the same thing that was on Input 4 clock cycles ago.

 
reg [3:0] Input_Delay;
 
always @(posedge clock)
  begin
    // Create a delayed version of signal Input
    Input_Delay    <= Input_Delay << 1;
    Input_Delay[0] <= Input;

    // FYI: Same Code not using Shift Operator:
    Input_Delay[1] <= Input_Delay[0];
    Input_Delay[2] <= Input_Delay[1];
    Input_Delay[3] <= Input_Delay[2];
    Input_Delay[0] <= Input;
 
    if (Input_Delay[3] == 1'b1)
      // Do Stuff
  end