Select Statement – VHDL Example

Assigning signals using Selected signal assignment

Select statements are used to assign signals in VHDL. They can only be used in combinational code outside of a process. A selected signal assignment is a clear way of assigning a signal based on a specific list of combinations for one input signal. The syntax is demonstrated in the example below. The signal name after with is the signal whose values are used to assign the output signal. The when others clause should always be used to avoid creating a latch by accident.

Note that if you try to put a select statement inside a process, you will get the error: Illegal sequential statement.

library ieee;
use ieee.std_logic_1164.all;

entity ex_select is
end ex_select;

architecture behave of ex_select is

  signal r_Index   : integer := 2;
  signal w_One_Hot : std_logic_vector(3 downto 0);
  
begin

  with r_Index select
    w_One_Hot <= "0000" when 0,
                 "0001" when 1,
                 "0010" when 2,
                 "0100" when 3,
                 "1000" when 4,
                 "0000" when others;
  
end behave;