How To Get A Job In FPGA – The Interview

JK, D, T. Further Reading: What is a Flip-Flop

SR, JK. Further Reading: What is a Latch

The main difference is that a Flip-Flop uses a clock as an input but a latch does not. The clock input on the flip-flop is used to pass the D input on the Flip-Flop to the Q output. A latch having no clock will latch or hold the output steady. In general, Flip-Flops are used commonly in FPGA designs and latches should be avoided.

FPGAs are highly customizable. Some reasons to use an FPGA in your design might be: many unique peripherals required, lots of input/output needed, very fast processing speed required, lots of math operations, high data throughputs, interfaces to high bandwidth external memory, and reprogrammability are common reasons.

A for loop in VHDL and Verilog is not the same thing as a for loop in python or C. In synthesizable code, for loops are used to replicate logic. It saves having to type the same thing over and over again, but it does not produce a loop in the same way that software programming loops work. In general, for loops should be avoided in synthesizable code for beginners unless they clearly understand how they work. Further Reading: For Loops in VHDL or Verilog.

SRAM means Static Random Access Memory, DRAM stands for Dynamic Random Access Memory. Both SRAM and DRAM are volatile, meaning that their information written to them is cleared when power is removed. However DRAM also needs to be “refreshed” in order to maintain the values written to it, where as SRAM being static does not need this. The refreshing is usually handled by the memory controller. As far as use-cases, SRAM is better when there are short non-sequential reads and writes to memory required, and DRAM is better when there are large burst reads/writes of sequential memory. For example if you’re reading 16-bits at a time from any random address in memory on each read, this is likely a better application for SRAM. But if you’re trying to store an entire image from a camera to memory this is definitely a better application from DRAM.

PLL stand for Phase-locked loop and is commonly used inside FPGAs to generate desired clock frequencies. PLLs are built-in to the FPGA fabric and are able to take an input clock and derive a unique out-of-phase clock from that input clock. They are very useful if your design requires several unique clocks to be running internally.

Inference is when you write VHDL or Verilog to “infer” or tell the synthesis tools to place some type of component down. For example, by creating a large memory storage register, you might be inferring a Block RAM. Instantiation is when you directly create the primitive component for the Block RAM based on the particular vendor’s user guide for how to instantiate primitive components. Inferrence is more portable across FPGA technologies. Instantiation might be better if you need to be very explicit about the primitive that you want to work with, or apply some unique settings to it.

Metastability means that a signal is in an unpredictable or unknown state. It occurs most often when bringing in a signal external to the FPGA into the internal logic. In general it should be avoided. There are several methods to prevent metastability inside your FPGA, a common suggestion is to “double-flop” all inputs into the local clock domain.

FIFO stands for First In First Out. It is a commonly used FPGA component. A FIFO is a storage element, usually made of a Block RAM for large FIFOs and registers for short FIFOs. They are used to buffer data, for example when reading and writing to external memory, or for when crossing clock domains, or for storing pixels coming out of a camera. Further Reading: What is a FIFO

A Block RAM is a specific part of an FPGA that is usually a 16k or 32k bits storage element. It can have dynamic width and depth and is useful for many applications inside of an FPGA. They are used in Dual-port memories, FIFOs, and LUTs to name a few. More Info: Block RAM in FPGA.

UART stands for Universal Asynchronous Receiver Transmitter. It is asynchronous, meaning there is no clock involved. It has the ability to both receive and transmit data serially. It is a low-bandwidth, low-pin-count, very simple interface that is commonly used to communicate between FPGAs, or from and FPGA to a microcontroller, or from an FPGA to a computer. Since there is no clock involved, the receiver and the transmitter need to agree on a baud rate and other parameters prior to communication. Further Reading: What is a UART?.

Synchronous means there is a clock involved, where as asynchronous means there is no clock. Most logic inside of an FPGA uses synchronous logic, like Flip-Flops, Block RAMs, etc, and things like Resets can be asynchronous. Separately, there can be both synchronous and asynchronous communication protocols. In general, most communication interfaces are synchronous (e.g. SPI, I2C, USB, etc), but a UART is asynchronous.

A shift register is a method of moving data from a source to a destination in some number of clock cycles. It is useful for creating delays inside of your FPGA, or for converting serial data to parallel data, or for converting parallel data to serial data. Further Reading: What is a Shift Register.

VHDL is strongly typed, commonly used for high-reliability code (e.g. military and medical devices). It is very verbose, meaning a lot of typing is required. Verilog is closer to C, is less strongly typed, and is generally more forgiving. Further Reading: VHDL vs. Verilog, which language should you learn first?.

Whenever crossing clock domains you should be concerned about creating a metastable condition. In general, it’s a good idea to use a primitive that is capable of crossing clock domains, such as a Block RAM, unless you’re careful with how you create your register logic and create timing constraints that tell the tools what you’re doing. Additionally, you want to make sure that your data storage element is deep enough to cross between the clock domains without losing data. This might happen if you write to a full FIFO or read from an empty FIFO, which happens when one clock domains is expecting data and there is none. Further Reading: Crossing Clock Domains in an FPGA.

Setup is the amount of time required for the input of a Flip-Flop to be stable before the clock edge comes along. Hold time is the amount of time required for the input of a Flip-Flop to be stable after the clock edge comes along. If setup or hold time is violated, then there can be a metastable condition inside of your FPGA. This will likely create a timing error inside the place and route tool. You should never have timing errors inside of an FPGA design. Further Reading: Setup and Hold Time in an FPGA.

Both melee and moore machines are types of state machines that can exist inside your FPGA. Melee machines depend on both the current state as well as inputs to know which state to go to next. Moore machines depend just on your current state to know which state to go to next. Personally, I find Moore machines simpler to code and understand, so I tend to use those.

The synthesis tools are provided by the FPGA vendor and are used to translate your VHDL or Verilog code into logic that the FPGA is built from (e.g. Flip-Flops, Look-Up Tables, Block RAMs, etc).

The synthesis process is usually followed by place and route, which takes the primitives and places them inside the FPGA and checks that the entire design meets your timing constraints. The timing constraints tell the FPGA the clock rates and the specific I/O to use, and the place and route process ensures that your design is able to work at those speeds.

SERDES stands for SERializer/DESerializer. These are high-speed transmitters and receivers that are used to send serial data across a point to point link. Usually these are used at speeds of > 1 Gbps. Current FPGA technology can have SERDES transceivers that operate at > 50 Gbps for a single data link. Data integrity at these speeds is very challenging, so lots of tricks are employed to ensure data is able to pass successfully. They are used commonly in RF applications, high-speed video applications, communication interfaces such as PCI Express, SATA, Gigabit Ethernet, etc.

DSP stands for Digital Signal Processor but it is really a dedicated piece of hardware inside the FPGA that is very good at performing fast multiplication and addition operations. Normal FPGA logic is able to perform multiplies, but not at fast data rates of say 200 MHz or faster. This is where dedicated DSP tiles are used. They are common in filter design or image processing pipelines that require many fast multiplication operations to be performed on input data.

Be prepared to talk in detail about your own experience using FPGAs! Have an interesting project to discuss. Bonus points if you put a link to a GitHub repository on your resume and show your source code.