Logical Operators – VHDL Example

Logical operators are fundamental to VHDL code. The logical operators that are built into VHDL are:

and, or, nand (my personal favorite), nor, xor, and xnor

These logical operators can be combined on a single line. Parenthesis will dictate the order of operations. For example the line:

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a <= (b and c) or (d and e);

Will first perform a logical “and” of signals b and c, then perform a logical “and” of signals d and e, then perform a logical “or” of the results of the two and operators. All of the logical operators are synthesizable. For reference here is a list of all of the truth tables of logical operators.

Below is the console output from running the code below in Modelsim:

# ** Note: AND  of 1 and 0 is '0'
# ** Note: OR   of 1 and 0 is '1'
# ** Note: NAND of 1 and 0 is '1'
# ** Note: NOR  of 1 and 0 is '0'
# ** Note: XNOR of 1 and 0 is '0'
# ** Note: AND  of 1 and 1 is '1'
# ** Note: OR   of 1 and 1 is '1'
# ** Note: NAND of 1 and 1 is '0'
# ** Note: NOR  of 1 and 1 is '0'
# ** Note: XNOR of 1 and 1 is '1'
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library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 
entity logical_operators is
end logical_operators;
 
architecture behave of logical_operators is
 
begin
 
  -- Logical Operator Demonstration Process
  process is
    variable v_A, v_B : std_logic;
    variable v_AND, v_OR, v_NAND, v_NOR, v_XOR, v_XNOR : std_logic;
  begin
    v_A    := '1';
    v_B    := '0';
    v_AND  := v_A and  v_B;
    v_OR   := v_A or   v_B;
    v_NAND := v_A nand v_B;
    v_NOR  := v_A nor  v_B;
    v_XNOR := v_A xnor v_B;
    report "AND  of 1 and 0 is " & std_logic'image(v_AND)  severity note;
    report "OR   of 1 and 0 is " & std_logic'image(v_OR)   severity note;
    report "NAND of 1 and 0 is " & std_logic'image(v_NAND) severity note;
    report "NOR  of 1 and 0 is " & std_logic'image(v_NOR)  severity note;
    report "XNOR of 1 and 0 is " & std_logic'image(v_XNOR) severity note;
    wait for 10 ns;
    v_A    := '1';
    v_B    := '1';
    v_AND  := v_A and  v_B;
    v_OR   := v_A or   v_B;
    v_NAND := v_A nand v_B;
    v_NOR  := v_A nor  v_B;
    v_XNOR := v_A xnor v_B;
    report "AND  of 1 and 1 is " & std_logic'image(v_AND)  severity note;
    report "OR   of 1 and 1 is " & std_logic'image(v_OR)   severity note;
    report "NAND of 1 and 1 is " & std_logic'image(v_NAND) severity note;
    report "NOR  of 1 and 1 is " & std_logic'image(v_NOR)  severity note;
    report "XNOR of 1 and 1 is " & std_logic'image(v_XNOR) severity note;
    wait;
  end process; 
 
end behave;

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