VHDL vs. Verilog

Which language should you use for your FPGA and ASIC designs?

The question of whether Verilog or VHDL is better for beginners is asked all the time. Both languages can be used to create code that runs on FPGAs and ASICs. Overall there are several points of which you should be aware.

1. VHDL is strongly typed. This makes it harder to make mistakes as a beginner because the compiler will not allow you to write code that is in valid. Verilog is weakly typed. It allows you to write code that is wrong, but more concise.
2. Verilog looks closer to a software language like C. This makes it easier for someone who knows C well to read and understand what Verilog is doing.
3. VHDL requires a lot of typing. Verilog generally requires less code to do the same thing.
4. VHDL is very deterministic, where as Verilog is non-deterministic under certain circumstances.

However none of these are the most important factor. You should learn VHDL or Verilog based on which one you are more likely to use in School or in Work. If your university uses Verilog, learn Verilog! If companies around you where you might want to work use VHDL, learn VHDL! The breakdown of who uses VHDL and Verilog is highly dependent on where in the world you are living. If you punch in VHDL versus Verilog into Google Trends, you can start to get a pretty good idea of which language you should be learning first.

From the above picture several things are interesting. The first is that the overall search volume on Google for VHDL and Verilog is about equal over the past year. This means that the two are roughly as popular for people looking for information about them. The second thing that I found interesting was that there is a huge dip right around Christmas/New Years. I can only assume that this is when people are not at school or work and therefore not Googling their HDL problems.

This picture shows a clearer breakdown of country by country VHDL vs. Verilog. India and the United States have the largest volume of Google searches, and VHDL and Verilog appear to be roughly equal in popularity in India, and Verilog is slightly more popular in the United States than VHDL. I know from personal experience that in the United States the defense industry favors VHDL generally, while commercial industry favors Verilog. Notice that in Germany and France, VHDL is significantly more popular than Verilog. If you are from either of these two countries, I would highly recommend learning VHDL first! In China and South Korea, we can see that Verilog is much more popular than VHDL, so adjust your priorities accordingly.

In general, VHDL and Verilog are equally capable languages. You should base your decision on which language to learn based on what’s most popular for your location and circumstances. Let’s start learning!

VHDL For Beginners, Start Learning VHDL!

Verilog For Beginners, Start Learning Verilog!