If Statement – VHDL Example

If statements are used in VHDL to test for various conditions. They are very similar to if statements in other software languages such as C and Java. There are three keywords associated with if statements in VHDL:

if, elsif, and else. Note the spelling of elsif!

The example below demonstrates two ways that if statements can be used. The first example is used in conjunction with a Generate Statement. The second example uses an if statement in a process. Both of these use cases are synthesizable.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

entity example_if_statement is
  generic (
    g_INIT : natural := 1        -- 0="DEAD", 1="BEEF"
    );
end example_if_statement;

architecture behave of example_if_statement is

  signal r_CHOICE : std_logic_vector(1 downto 0)  := "00";
  signal r_VECTOR : std_logic_vector(15 downto 0) := (others => '0');
  
begin

  -- If statement outside of a process (requires generate keyword)
  g_IF_SETTING_1 : if g_INIT = 0 generate
    r_VECTOR <= X"DEAD";
  end generate g_IF_SETTING_1;

  g_IF_SETTING_2 : if g_INIT = 1 generate
    r_VECTOR <= X"BEEF";
  end generate g_IF_SETTING_2;

  
  -- If statement inside of a process
  p_IF_TEST : process (r_VECTOR) is
  begin 
    if r_VECTOR = X"DEAD" then
      r_CHOICE <= "01";
    elsif r_VECTOR = X"BEEF" then
      r_CHOICE <= "10";
    else
      r_CHOICE <= "11";
    end if;
  end process p_IF_TEST;
  
end behave;