Entity and Architecture – VHDL Example

If this is the first time you have looked at VHDL Code before, you should start with a tutorial geared for beginners.

The entity/architecture combination is the most fundamental building block in VHDL. Entities and Architectures are used together to define a piece of functionality. There should only be one entity and architecture for each file. Often a large FPGA design is broken into many entity/architect combinations. The entity contains the port map. The port map is used to define all input and output signals for a particular entity.

Signals can be one of three types: in, out, and inout. In and Out are self-explanatory, inout is a bidirectional signal that can be either an input or an output. In general, inouts should not be used until you gain some confidence in your FPGA designs, as they are more involved.

An entity can also contain a generic map in addition to a port map. Generics are used to pass constants into an entity from a higher level. An example of generics is helpful to see how they are used.

The example below uses two inputs, each of which is declared as type std_logic. There is a process that performs the and function and stores the output in the signal o_bit. There is an additional file that is known as a test bench. It serves to exercise the functionality in the entity under test.

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library ieee;
use ieee.std_logic_1164.all;

entity example_entity_architecture is
  port (
    i_bit_1 : in  std_logic;
    i_bit_2 : in  std_logic;
    o_bit   : out std_logic
    );  
end example_entity_architecture;

architecture behave of example_entity_architecture is

begin

  p_PROCESS: process (i_bit_1, i_bit_2) 
  begin

    o_bit <= i_bit_1 and i_bit_2;

  end process p_PROCESS;
  
end behave;