VHDL Configuration Example

Configurations are an advanced concept in VHDL, but they can be very useful when used properly. They allow the designer to specify different architectures for a single entity. In other words, the internals of a design can change while the interface remains the same. Configurations are not required to get a basic VHDL design running, therefore unless you have a compelling reason to use them, I recommend beginners avoiding them.

Configurations can be used for any one of the following reasons:

• • Directed Testing. Swapping between different directed test architectures is a good use of configurations. When writing simulations, the same port map can be used to design many directed tests. The simulation can choose the desired directed test to execute using configurations.
  • Using Bus Functional Models (BFMs). Occasionally large projects get going by inserting BFMs rather than RTL code. Once the actual RTL code gets written, these BFMs can be swapped out and replaced with the actual RTL code by using configurations.
  • Testing Unusual Behavior. If you want to stress a certain part of your design with erroneous behavior, an architecture that is designed to behave erroneously can be binded to your entity. This is useful in simulations for finding strange corner cases in a design.
  • Increasing Simulation Speed. Swapping out large RTL code for barebones or empty code in the interest of simulation speed is a very handy use for configurations. The more signals to simulate, the slower the simulation will run. By swapping out large architectures for smaller ones, your sim time will improve.

configuration CONFIGURATION_NAME of INSTANTIATING_ENTITY is
  for INSTANTIATING_ARCH 
    for INSTANCE_NAME : COMPONENT_NAME
      use entity LIBRARY_NAME.ENTITY_NAME(ARCHITECTURE_NAME);
    end for;
  end for;
end CONFIGURATION_NAME;

The example below demonstrates how to use a configuration to bind a specific entity to a specific architecture.

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library ieee;
use ieee.std_logic_1164.all;

entity HA_Entity is
  port (
    i_bit1  : in std_logic;
    i_bit2  : in std_logic;
    --
    o_sum   : out std_logic;
    o_carry : out std_logic
    );
end HA_Entity;


architecture HA_Arch of HA_Entity is

  component HA_Comp is
    port (
      i_bit1  : in  std_logic;
      i_bit2  : in  std_logic;
      --
      o_sum   : out std_logic;
      o_carry : out std_logic
      );
  end component HA_Comp;

begin

  HA_Inst : HA_Comp
    port map (
      i_bit1  => i_bit1,
      i_bit2  => i_bit2,
      o_sum   => o_sum,
      o_carry => o_carry);

end HA_Arch;


library ieee;
use ieee.std_logic_1164.all;

entity HA_Comp_Entity is
  port (
    i_bit1  : in std_logic;
    i_bit2  : in std_logic;
    --
    o_sum   : out std_logic;
    o_carry : out std_logic
    );
end HA_Comp_Entity;

architecture HA_Comp_Arch_1 of HA_Comp_Entity is
begin

  o_sum   <= i_bit1 xor i_bit2;
  o_carry <= i_bit1 and i_bit2;

end HA_Comp_Arch_1;


use work.all;

configuration HA_Config of HA_Entity is
  for HA_Arch
    for HA_Inst : HA_Comp
      use entity HA_Comp_Entity(HA_Comp_Arch_1);
    end for;
  end for;
end HA_Config;