Concatenation Operator – Verilog Example

The Verilog concatenate operator is the open and close brackets {, }. It should be mentioned that these brackets can also be used to do replication in Verilog, but that is for another example. Concatenation can be used to combine two or more types together. In Verilog, the signals that are being concatenated do not need to be of the same type. VHDL is more strongly typed, so concatenation in VHDL requires that types are matched.

Additionally, widths in Verilog do not have to match. For example, you can concatenate 2 signals that are 4 bits wide into a signal that is 16 bits wide. Verilog will pad the upper 8 bits with zeros. VHDL does not allow this, the input width must exactly match the width of the signal you are trying to assign.

Concatenation is used frequently when designing shift registers. The example below demonstrates a 1 being shifted continuously through an 8-bit register. This would be an efficient way to grant arbitration to one of 8 requesting modules at any given time. Shift registers are also often used to turn parallel data into serial data, for example in a UART.

Below is the console output from running the code below in Modelsim:

# Concatenation of 7 and c is 7c
# Concatenation of e and 2 is e2
# Concatenation of two 4-bit regs into a 16-bit reg: 007c
# Complete

concatenation_operator.v:

module concatenation_operator();
  reg [3:0]  r_VAL_1 = 4'b0111;
  reg [3:0]  r_VAL_2 = 4'b1100;
  wire [7:0] w_CAT;

  reg  [3:0]       r_UNSIGNED = 4'b0010;
  reg signed [3:0] r_SIGNED   = 4'b1110;
  wire [7:0] 	   w_CAT_2;
  wire [15:0] 	   w_CAT_3;
  
  reg              r_CLOCK = 1'b0; 
  reg [7:0]        r_SHIFT_REG = 8'h01;
  
  // Demonstrates a common concatenation.
  assign w_CAT = {r_VAL_1, r_VAL_2};

  // Demonstrates concatenation of different types
  assign w_CAT_2 = {r_SIGNED, r_UNSIGNED};

  // Demonstrates Verilog padding upper bits with 0.
  assign w_CAT_3 = {r_VAL_1, r_VAL_2};

  initial 
    begin
      #5;
      $display("Concatenation of %h and %h is %h", 
	       r_VAL_1, r_VAL_2, w_CAT);
      #20;
      $display("Concatenation of %h and %h is %h", 
		 r_SIGNED, r_UNSIGNED, w_CAT_2);
      #20;
      $display("Concatenation of two 4-bit regs into a 16-bit reg: %h",  
               w_CAT_3);
      
      #20;
      $display("Complete");
    end

  
  // Generate a clock to drive shift register below
  always #1 r_CLOCK = !r_CLOCK;

  // Demonstrate Shifting of a 1 through an 8 bit register.
  always @(posedge r_CLOCK)
    begin
      r_SHIFT_REG[7:0] <= {r_SHIFT_REG[6:0], r_SHIFT_REG[7]};
    end
  
endmodule // concatenation_operator