How to avoid creating a Latch
Tutorial - How to avoid creating Latches in your [...]
VHDL Math: std_logic_arith vs. numeric_std
Std_logic_arith vs. Numeric_std Have you ever tried to do [...]
What is a Testbench?
Tutorial - What is a Testbench How Testbenches are [...]
Coding Style Guidelines for VHDL & Verilog
Code Guidelines for VHDL and Verilog Below are the [...]
Blocking vs. Nonblocking in Verilog
Blocking vs. Nonblocking in Verilog The concept of Blocking [...]
Create Tri-State Buffer in VHDL and Verilog
Tutorial - What is a Tri-State Buffer Why are [...]
Debounce a Switch
How to Debounce a Switch in an FPGA Fix [...]
Lots more VHDL and Verilog Modules!
VHDL and Verilog Completed Modules All of the modules, [...]
UART (RS-232, Serial Port, COM Port)
What is a UART? AKA Serial Port, RS-232, COM [...]
Lesson 1: What is an FPGA?
Meet the FPGA An FPGA, short for field programmable [...]