Arrays – VHDL Example

Create your own types using arrays

Arrays are used in VHDL to create a group of elements of one data type. Arrays can only be used after you have created a special data type for that particular array. Below are some rules about arrays.

• Arrays can be synthesized
• Arrays can be initialized to a default value
• Array type definitions can be unconstrained (undefined length)
• Arrays of arrays are allowed (e.g. an array of std_logic_vector)
• Two-Dimensional (2D) arrays are allowed
• Signals and Variables can be declared as an array type

Creating An Array:

-- Creates a simple array of bytes, 128 bytes total:
type t_Memory is array (0 to 127) of std_logic_vector(7 downto 0);
signal r_Mem : t_Memory;

-- Creates an unconstrained array (MUST be constrained when defined!)
type t_Integer_Array is array (integer range <>) of integer;
variable r_Integers : t_Integer_Array(0 to 15);

Initializing An Array:

type t_Data is array (0 to 3) of std_logic;
signal r_Data : t_Data := (Bit1, Bit2, Bit3, Bit4);

type t_Multiplier is array (0 to 2) of real;
signal r_Multiplier : t_Multiplier := (0.25, 0.5, 0.75);

-- Initializing an array of an array:
type t_Five is array (0 to 4) of bit_vector(15 downto 0);
signal r_Calc : t_Five := (others => (others => '0'));

Creating a Two-Dimensional (2D) Array

-- Creates a 4x3 array for a number pad
type t_Row_Col is array (0 to 3, 0 to 2) of integer range 0 to 9;
signal r_Number : t_Row_Col;

-- Accessing The Array:
r_Choice <= r_Number(0, 1);

r_Number(3, 2) <= 9;