Replication Operator – Verilog Example

The Verilog replication operator is the open and close brackets {, }. It should be mentioned that these brackets can also be used to do concatenation in Verilog, but that is for another example. The replication operator is used to replicate a group of bits n times.

The number in front of the brackets is known as the repetition multiplier. So for example, in {3{2’b01}} 3 is the repetition multiplier and 2’b01 is what will be replicated 3 times. It is important to note that the repetition multiplier must be a constant. The compiler will throw the error: Repetition multiplier must be constant if this is not true.

Below is the console output from running the code below in Modelsim:

# Replication of 0x7, 3 times is 0x777
# Replication of 0x7, 2 times is 0x77
# Concatenate 4 with replication of 0xA twice: 0x4aa
# Replicate the concatenation of 0xB and 0xC 4 times: 0xbcbcbcbc
# ** Note: $finish    : example_replication_operator.v(32)

replication_operator.v:

module replication_operator();
  reg [3:0]  r_VAL_1 = 4'b0111;
  
  parameter c_MULTIPLIER = 4'b0010;
    
  initial 
    begin

      // Replication Only
      $display("Replication of 0x7, 3 times is 0x%h", 
	       {3{r_VAL_1}});

      // Replication is possible using a constant (parameter)
      // Note that replication multiplier CANNOT be a reg
      $display("Replication of 0x7, %1d times is 0x%h",
	       c_MULTIPLIER, {c_MULTIPLIER{r_VAL_1}});

      // Replication and Concatenation together
      $display("Concatenate 4 with replication of 0xA twice: 0x%h",
               {4'h4,{2{4'hA}}});

      // Replication and Concatenation 2
      $display("Replicate the concatenation of 0xB and 0xC 4 times: 0x%h",
               {4{4'hB, 4'hC}});

      #20;
      $finish;
    end
endmodule // replication_operator