Repeat Loop – Verilog Example

A repeat loop in Verilog will repeat a block of code some defined number of times. It is very similar to a for loop, except that a repeat loop’s index can never be used inside the loop. Repeat loops just blindly run the code as many times as you specify.

Repeat Loops can be used synthesizable code, but be careful with them!. They should only be used to expand replicated code. See the example on For Loops for more detail on how this works. More often, repeat loops are used in testbenches.

Note that the Jump Statements return and break can be used to exit your loop prematurely, but these are only supported in SystemVerilog.

repeat_example.v:

module repeat_example (); 

  reg r_Clock = 1'b0;
  
  initial 
    begin

      repeat (10)
        #5 r_Clock = !r_Clock;

      $display("Simulation Complete");
    end
endmodule