Records – VHDL Example

The Record construct in VHDL can be used to simplify your code. Records are similar to structures in C. Records are most often used to define a new VHDL type. This new type contains any group of signals that the user desires. Most often this is used to simplify interfaces. This is very handy with interfaces that have a large list of signals that is always the same. For example interfaces to an off-chip memory might be large and have the same signals over and over throughout your design. Records can be used to shrink the code size and have less signals in your entity to maintain. The designer simply needs to define the record type in a single package file, then use the package file for any entity that makes use of that record type.

The example below creates two record types in a package file (example_record_pkg.vhd). These types are used in example_record.vhd to simplify a FIFO interface. One signal of type t_FROM_FIFO is created for all inputs from the FIFO and a separate signal of type t_TO_FIFO is created for all outputs to the FIFO.

Summary:

1. Records are used to simplify entities and port maps in VHDL.
2. Records may contain elements of different types. (std_logic, integer, etc)
3. Records are similar to structures in C.
4. Records used across multiple files should be kept in a single package file.
5. Signals defined as records can be initialized.
6. It is possible to create an array of records.

library ieee;
use ieee.std_logic_1164.all;

package example_record_pkg is

  -- Outputs from the FIFO.
  type t_FROM_FIFO is record
    wr_full  : std_logic;                -- FIFO Full Flag
    rd_empty : std_logic;                -- FIFO Empty Flag
    rd_dv    : std_logic;
    rd_data  : std_logic_vector(7 downto 0);
  end record t_FROM_FIFO;  

  -- Inputs to the FIFO.
  type t_TO_FIFO is record
    wr_en    : std_logic;
    wr_data  : std_logic_vector(7 downto 0);
    rd_en    : std_logic;
  end record t_TO_FIFO;

  constant c_FROM_FIFO_INIT : t_FROM_FIFO := (wr_full => '0',
                                              rd_empty => '1',
                                              rd_dv => '0',
                                              rd_data => (others => '0'));

  constant c_TO_FIFO_INIT : t_TO_FIFO := (wr_en => '0',
                                          wr_data => (others => '0'),
                                          rd_en => '0');
  
  
end package example_record_pkg;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

use work.example_record_pkg.all; -- USING PACKAGE HERE!

entity example_record is
  port (
    i_clk  : in  std_logic;
    i_fifo : in  t_FROM_FIFO;
    o_fifo : out t_TO_FIFO := c_TO_FIFO_INIT  -- intialize output record
    );
end example_record;

architecture behave of example_record is

  signal r_WR_DATA : unsigned(7 downto 0) := (others => '0');
  
begin

  -- Handles writes to the FIFO
  p_FIFO_WR : process (i_clk) is
  begin 
    if rising_edge(i_clk) then
      if i_fifo.wr_full = '0' then
        o_fifo.wr_en   <= '1';
        o_fifo.wr_data <= std_logic_vector(r_WR_DATA + 1);
      end if;
    end if;
  end process p_FIFO_WR;
  
  -- Handles reads from the FIFO
  p_FIFO_RD : process (i_clk) is
  begin 
    if rising_edge(i_clk) then
      if i_fifo.rd_empty = '0' then
        o_fifo.rd_en <= '1';
      end if;
    end if;
  end process p_FIFO_RD;
  
end behave;