Case Statement – VHDL Example

The VHDL Case Statement works exactly the way that a switch statement in C works. Given an input, the statement looks at each possible condition to find one that the input signal satisfies. They are useful to check one input signal against many combinations.

Just like in C, the VHDL designer should always specify a default condition provided that none of the case statements are chosen. This is done via the “when others =>” statement. See the code below for an example of this.

One annoyance with case statements is that VHDL does not allow the use of less than or greater than relational operators in the “when” condition. Only values that are equal to the signal in the case test can be used.

A note about synthesis: When case statements are synthesized by the tools, they generate optimized decode logic to quickly select which case statement is valid. They are more efficient than using if/elsif statements because if/elsif can generate long carry-chains of logic that can cause difficulties meeting timing.

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library ieee;
use ieee.std_logic_1164.all;

entity example_case_statement is
end example_case_statement;

architecture behave of example_case_statement is

  signal r_VAL_1  : std_logic := '0';
  signal r_VAL_2  : std_logic := '0';
  signal r_VAL_3  : std_logic := '0';
  signal r_RESULT : integer range 0 to 10;
  
begin


  -- Uses r_VAL_1, r_VAL_2, and r_VAL_3 together to drive a case statement
  -- This process is synthesizable
  p_CASE : process (r_VAL_1, r_VAL_2, r_VAL_3)
    variable v_CONCATENATE : std_logic_vector(2 downto 0);
  begin
    v_CONCATENATE := r_VAL_1 & r_VAL_2 & r_VAL_3;
    
    case v_CONCATENATE is
      when "000" | "100" =>
        r_RESULT <= 0; when "001" =>
        r_RESULT <= 1; when "010" =>
        r_RESULT <= 2; when others =>
        r_RESULT <= 9;
    end case;
    
  end process;


  -- This process is NOT synthesizable.  Test code only!
  -- Provides inputs to code and prints debug statements to console.
  p_TEST_BENCH : process is
  begin
    r_VAL_1 <= '0';
    r_VAL_2 <= '0';
    r_VAL_3 <= '0';
    wait for 100 ns;
    r_VAL_2 <= '0';
    r_VAL_3 <= '1';
    wait for 100 ns;
    r_VAL_2 <= '1';
    r_VAL_3 <= '0';
    wait for 100 ns;
    r_VAL_2 <= '1';
    r_VAL_3 <= '1';
    wait for 100 ns;
    wait;
  end process;
  
end behave;